1. Field of the Invention
The present invention relates to an active matrix substrate in which a plurality of pairs of a thin film transistor (which is abbreviated as “TFT”) and a pixel electrode are arranged in an array, and a liquid crystal device including the same.
2. Description of Related Art
An electro-optic device such as an active matrix type liquid crystal device or an organic electroluminescence (EL) device which uses a thin film transistor (TFT) as a pixel switching element is utilized as a flat panel display or the like for its advantage of low power consumption and thin thickness.
The flat panel display is expected to move to further upsizing and higher definition (HD), which will lead to an increase in the need for a TFT having higher driving capability than an amorphous silicon TFT (a-Si TFT) that has been commonly used as an image switching element.
As the TFT having higher driving capability than the a-Si TFT, a crystalline silicon TFT such as a polycrystalline silicon TFT (pc-Si TFT) or a microcrystalline silicon TFT (μ-Si TFT) is under review.
In recent years, in order to achieve a narrower frame and cost reduction of the liquid crystal device or the EL device, a driver circuit integral type in which a driver circuit such as a source driver or a gate driver using a drive TFT is formed on the same substrate as a pixel area having a pixel switching TFT has been developed. By forming the driver circuit on the same substrate as the pixel area, the cost of an external IC chip can be reduced, and the frame can be narrowed because there is no need for an IC chip mounting area.
Because a higher drive voltage is applied for a longer period of time to the drive TFT compared to the pixel switching TFT, degradation of electrical characteristics increases. In such an application as well, a crystalline silicon TFT such as a polycrystalline silicon TFT (pc-Si TFT) or a microcrystalline silicon TFT (μc-Si TFT) with high reliability and high mobility is suitably used.
Because a trap density and a defect level due to crystal defect are suppressed in the crystalline silicon film such as pc-Si or μc-Si, use of such a film enables obtainment of a TFT having good device characteristics with low threshold voltage shift and high field-effect mobility.
Particularly, μc-Si has uniform crystals with a crystal size of 100 nm or less in general, and use of μc-Si reduces variation of TFT device characteristics, which is preferable.
As a method of forming a crystalline Si film such as pc-Si or μc-Si, a method that forms an a-Si film and then poly-crystallizes the a-Si film by laser annealing that applies laser light (cf. Claim 1 etc. of Japanese Unexamined Patent Application Publication No. 2003-17505) and a method that deposits a μc-Si film directly by plasma chemical vapor deposition (CVD) (cf. Paragraph 0041 etc. of Japanese Unexamined Patent Application Publication No. H08-97436) are known.
As a pixel switching TFT of a liquid crystal device, an inverted staggered TFT is widely used. Further, a plurality of photolithography process steps are necessary to manufacture a TFT, and it is desirable to reduce the number of photolithography process steps. Therefore, a back-channel-etch type that etches a channel backside is often used in the inverted staggered TFT because it can be manufactured with a relatively small number of photolithography process steps.
In the case of using a crystalline Si film such as a pc-Si film or a μc-Si film as a channel layer in the above-described back-channel-etch type TFT, an a-Si film is generally laminated thereon. This is for the following reason.
When the back-channel etching is performed, it is very difficult to ensure the etching selectivity between the ohmic contact layer (n-layer) connected to the source/drain electrode and the semiconductor film of the channel layer. Therefore, it is necessary to set the thickness of the semiconductor film in the channel layer to be thick and set an etching time to be long enough in consideration of variation of the film thickness of the n-layer in a substrate plane or variation of an etching rate.
However, in the method of poly-crystallizing the a-Si film by laser annealing which is disclosed in Japanese Unexamined Patent Application Publication No. 2003-17505, if the a-Si film which is formed first is deposited to be thick, the a-Si film cannot be molten enough to the lower part, and it is thus difficult to form a crystalline Si film having good crystallinity all over the thickness direction to the interface with a gate insulating film. Further, in the method of depositing the μc-Si film directly by plasma CVD which is disclosed in Japanese Unexamined Patent Application Publication No. H08-97436, because a deposition rate of the μc-Si film is very low, throughput decreases significantly to obtain a sufficient thickness.
In view of the above, a technique is employed which ensures a process margin for back-channel-etching by laminating an a-Si film with a relatively high deposition rate on a crystalline Si film formed by laser annealing or plasma CVD.
Although the TFT using a crystalline Si film such as a pc-Si film or a μc-Si film has higher driving capability than the a-Si TFT, it has an issue that leakage current is likely to occur compared to the a-Si TFT. This is for the following reason.
The back-channel-etch type inverted staggered a-Si TFT has a structure in which the side face of the a-Si film being a channel layer is in direct contact with a source electrode and a drain electrode. If this structure is applied as it is to the TFT using a crystalline Si film, a structure is such that the crystalline Si film with higher hole mobility than the a-Si film is in direct contact with the source electrode and the drain electrode.
In order to turn off the TFT, a reverse bias negative voltage is applied to a gate electrode, and, at this time, a high electric field is generated between the gate electrode and the source/drain electrode, so that a hole is injected to the crystalline Si film. In the structure in which the crystalline Si film with higher hole mobility than the a-Si film is in direct contact with the source electrode and the drain electrode, leakage current from the crystalline Si film is likely to flow into the source electrode and the drain electrode compared to the a-Si TFT.
Further, in a transmissive liquid crystal display device, light is applied from a backlight during image display. When light is applied to the crystalline Si film, an electron-hole pair is created in the film, and a positive hole moves when the gate electrode is at a negative voltage, and light leakage current is thereby generated. The leakage current flowing during the off-state of the TFT causes a loss of charges written to a pixel electrode, which can lead to display defect.
FIGS. 7(b) and 7(c) of T. Kaitoh et. al, “SELAX Technology for Poly-Si TFTs Integrated with Amorphous-Si TFTs”, SID Tech. Dig., 2008, p. 1066-1069 disclose a structure in which the upper face and the side face of a laminated film of a pc-Si film and an a-Si film are covered with an ohmic contact layer made of a Si film doped with an impurity, so that the pc-Si film is not in direct contact with a source electrode and a drain electrode. This structure is applicable to a TFT which includes a channel layer having a laminated structure of a μc-Si film and an a-Si film.
In the structure shown in FIGS. 7(b) and 7(c) of T. Kaitoh et. al, the ohmic contact layer made of an Si film doped with an impurity is formed protruding to the outside of a gate electrode, and light from a backlight is applied to that part. Therefore, an electron-hole pair is created in the ohmic contact layer by the application of light, and a positive hole moves when the gate electrode is at a negative voltage, and light leakage current is thereby generated.
Further, even when the ohmic contact layer made of a Si film doped with an impurity is interposed between the laminated film of the pc-Si film and the a-Si film and the source/drain electrode, it is not possible to sufficiently prevent a positive hole generated in the crystalline Si film when the gate electrode is at a negative voltage from flowing to the source and drain electrodes.